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Product Introduction
Functional Features
ECC and data integrity protection
Design flexibility

Product Introduction

With the development of semiconductor technology, the capacity density of non-volatile storage (NVM) media represented by NAND flash memory continues to increase, and the capacity cost continues to decrease. At the same time, it also has advantages such as fast random access response and high aggregate throughput. SSD based on NAND flash memory has become an ideal option to store active data in the system instead of replace mechanical disks.

TAI is an NVMe SSD controller designed by DERA for enterprise and data center, based on data reliability assurance and flash memory performance aggregation core technology. TAI controller supports up to 16 NAND channels and mainstream device models from multiple NAND manufacturers, at the same time provides flexible configuration options. Based on TAl controller, developers can build enterprise NVMe SSDs with leading reliability and performance.

PCIe Gen3x4

16 NAND channels

Up to 16TB capacity

Support mainstream NAND flash

Functional Features

NVMe 1.3 compliance, support PCIe Gen3 x4
Support NVMe optional command and vendor specific command, realize customized firmware
Support mainstream NAND flash, support both ONFI and TOGGLE
512GB-16TB total raw-capacity
16 NAND channels, 1.8V/1.2V VCCQ, 533MT/s I/O speed. Up to 16 NAND Dies per channel
Up to 5GB/s/ 4GB/s sequential read/ write bandwidth, up to 4KB random read 1M IOPS
Dual channels 40bit DDR controller with ECC protection, DDR3/3L 1333MT/s, up to 16GB DRAM
Support AES256 hardware encryption
SPI NOR with ECC protection, multiple general interfaces: 5*UART, 2*I2C, 16*GPIO and 2*SPI
All internal RAM protected by ECC, whole end-to-end CRC data path protection

ECC and data integrity protection

The TAI's built-in ECC engine provides powerful error detection and correction capabilities, and provides a certain configuration flexibility. You can choose between multiple functional gears according to actual needs and restrictions. The highest error correction capability of the ECC engine is 512Bytes/100bits, and other available levels are 1KB/40bits, 1KB/60bits, 1KB/72bits, 1KB/80bits, 1KB/100bits. Each NAND channel has its own ECC unit, ensure sustained low latency and high I/O bandwidth when multiple channels parallel accessing.

Besides NAND LDPC protection, the TAI controller also provides ECC protection to external DRAM and internal SRAM, and whole end-to-end CRC data path protection.

In some cases, NAND may occur uncorrectable error, especially when NAND going to the end of lifetime. To ensure data safety and keep high I/O performance, the TAI controller provides hardware RAID acceleration function. Under the control of firmware, multiple NAND Dies build adaptive RAID group, help to recover data base on other Dies' data within the RAID group when uncorrectable error occurs.

Design flexibility

The TAI controller provides flexible design options, so developer could customize software to reach the balance among cost, power and performance.

With target requirement and product definition, developer could make choice at ECC strength，NAND channel number/ capacity，DRAM channel number/ capacity，DRAM ECC on/ off，DRAM and/ or NAND interface, till getting an optimized solution.